The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing the semiconductor integrated circuit device. More particularly, the present invention relates to a technique effectively applied to a semiconductor integrated circuit device having: a highly integrated memory circuit using a spacer made of a silicon oxide film and a silicon film; and a logic embedded memory in which a memory circuit and a logic circuit are provided on the same semiconductor substrate, and applied to a production method thereof.
In the conventional logic embedded memory in which the DRAM (Dynamic Random Access Memory) and the logic circuit are provided on the same semiconductor substrate, a type polycrystalline silicon film whose a conductivity type is an n type has been used for the gate electrode of an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor).
However, in order to improve the operation speed of the entire DRAM and continue to store data in a memory cell, the research and circuit design about various structures and circuit designs have been performed because of an improvement of a so-called refresh characteristic, that is, a characteristic of refreshing regularly the memory contents thereof.
Also, there has been the problem of enhancing the threshold voltage of a memory cell selecting MISFET in the memory cell. As the specific solution thereof, for example, Japanese Patent Laid-open No. 2000-174225 has disclosed that a polycrystalline silicon whose a conductivity type is a P type is used for gate electrodes of an n channel memory cell selecting MISFET and a p channel MISFET constituting the peripheral circuit of the DRAM.